Viability of Low Temperature Deep and Ultra Deep Submicron Scaled Bulk nMOSFETs on Ultra Low Power Applications

Chip cooling is an attractive option for leakage control and power as well as thermal management of high performance ICs. Subthreshold leakage being the main leakage contributor in nanoscale CMOS, it rapidly increases with scaling due to continuous reduction in the supply voltage and is highly temperature sensitive. The authors in this work investigate Si bulk nMOSFETs using both constant voltage scaling as well as constant field scaling rules where temperature is employed as a design variable to improve subthreshold characteristics in the deep and ultradeep submicron regions of operation. Devices of gate lengths 90nm, 65nm in the deep submicron, and 45nm, 32nm in the ultradeep submicron region are designed using 2D Silvaco ATLAS device simulator. Encouraging subthreshold characteristics in the 150K-300K range are achieved. The optimum temperature at which these scaled devices would produce best subthreshold slope and maximum reduction in the OFF state leakage current is also suggested. Minimizing power consumption than pure subthreshold operation being a major concern, standby power is estimated at the optimized temperature to compare the scaling effects. This work recommends the 45nm device to be used for both ULP and HP applications at 200K.